The present invention relates to a method of monitoring an erase threshold voltage distribution in a NAND flash memory device. More particularly, the present invention relates to a method of monitoring an erase threshold voltage distribution in a NAND flash memory device for accurately measuring an erase threshold voltage distribution through an interference correlation between a peripheral cell and a main cell.
Recently, the demand has increased for a semiconductor memory device which electrically programs and erases data, and does not require a refresh function of periodically rewriting data.
In addition, a high integration technique of a memory cell has been developed for a mass storage memory device for storing a large amount of data. For example, a NAND flash memory where cells are connected in series to form a string for a highly integrated memory cell has been developed.
The NAND flash memory device controls a threshold voltage of the memory cell by injecting electrons into a floating gate of the memory cell or by emitting electrons in the floating gate by using an F-N tunneling method, thereby performing program and erase operations.
Since a multi-level cell in the NAND flash memory has a plurality of threshold voltage distribution conditions (unlike a single level cell), the multi-level cell should have an adequate read margin between threshold voltage distribution conditions.
Additionally, a shift phenomenon of the threshold voltage due to an interference effect of elements affecting the threshold voltage exists in the NAND flash memory device employing the floating gate. To reduce the shift phenomenon, a width of the threshold voltage distribution in each of the conditions is decreased. As a result, a maximum program threshold voltage is reduced. Accordingly, programming time is decreased due to the reduction of the maximum program threshold voltage, thereby enhancing program throughput.
However, the shift change of the threshold voltage due to the interference effect has a higher value as a quantity of change of a threshold voltage of a peripheral cell is increased. Thus, the quantity of change of the threshold voltage of the peripheral cell should be reduced as much as possible. Accordingly, there is a need to reduce the width of the threshold voltage of an erased cell. There is also a need to dispose a minimum erase threshold voltage next to a read line of the erased cell.
However, the threshold voltage of the erased cell has a negative value and the NAND flash memory device is activated by a positive bias. Thus, it is difficult to measure a negative threshold voltage value. On the other hand, it is possible to measure the threshold voltage having a negative value under negative bias conditions, but the size of a chip may be increased. Therefore, the NAND flash memory predicts the distribution of the negative threshold voltage value through an erase verifying operation performed at 0V after an erase operation.
Since it is difficult to accurately monitor the erase threshold voltage distribution, it is challenging to verify whether or not the erase threshold voltage distribution is improved through a process skew control. Furthermore, it is difficult to verify the erase threshold voltage distribution while performing a post program operation after erasing to improve the interference effect. Moreover, it is hard to verify a level of a threshold voltage of a program disturb tail bit.